Optimum design of Viterbi decoder for high speed data telecommunication receivers with 802.16a case study

In this paper, we present a floating-point model for OFDM part of the IEEE 802.16a standard. This part has been assigned as the mandatory structure for WiMax. Next, we present a bit-true model for Viterbi decoder and encoder of it with the constraint of having less than 0.5 dB degradation in the performance of the system while minimizing the hardware cost of it. Since the most sensitive modulation in the standard is 64QAM with the rate 5/6 for convolution coding, it has been used for bit-true modeling. While all of the system blocks are floating-point, we have extracted the BER of the ideal system under different channel noises with random binary input data and AWGN noise. We have validated our model by comparing its results with those of analytical formulas which are driven for AWGN channel noise. We have developed the bit-true model of the Viterbi block and have tuned the system to satisfy all of the standard requirements and the condition of less than 0.5 dB degradation in the performance at the worst case. This 0.5 dB condition is used in many papers as the implementation marginal value. Finally, the bit-true parameters of this experience can be used for different hardware realization structures (fixed-point or floating-point). Also samples of the input and output data of each block in the bit-true model can be used as a test bench for the same hardware structure. The final Viterbi decoder designed with traceback depth equal to 50 and 8 bit soft decision.