Parallel architectural scheme for transporting clock, data and synchronization for OC-192 using WDM

We propose a parallel architectural scheme that allows the transmission of data in a truly parallel format at OC-192 and higher rates. The parallel signals consist of clock, frame synchronization pulse and byte wide data bits. The clock signal is transported by using the least dispersed wavelength, λ₀, like any other data signal. Therefore, simultaneous transmission of clock with data eliminates the need for clock recovery circuitry and special encoding of data using scramblers. The synchronization pulse and the byte wide data bits are transported over wavelengths λ₁...λ _n which are adjacent to λ₀. The synchronization pulse is used in acquiring and maintaining frame sync. The simultaneous byte wide data, clock and sync. pulse transportation besides lowering the operating frequency of the electronics from 10 Gb/s to 1.25 Gb/s also eliminates the need for byte alignment