Title :
Realization of a monochip Viterbi decoder in ASIC technology
Author_Institution :
Alcatel Transmission Faisceaux Hertziens, Levallois-Perret, France
fDate :
30 Sep-3 Oct 1990
Abstract :
An ASIC realization of a Viterbi decoder is presented for the convolutional code of rate 1/2 and constraint length 7 (generator polynomials 133 and 171) and the code derived from it by puncturing to provide a code of rate 3/4, or by reuse of the same polynomials to get codes of rate 1/4 and 1/8. The technology is CMOS 1.5 μm, and the chip size is 14×14 mm2. It contains about 45000 gates plus 3 three-port RAMs. The maximum user data rate of the chip in industrial worst-case conditions at 17 Mbit/s. The circuit is comprised of a coder and a decoder whose characteristics are described
Keywords :
CMOS integrated circuits; application specific integrated circuits; codecs; decoding; digital integrated circuits; 1.5 μm CMOS technology; 1.5 micron; 17 Mbit/s; ASIC; RAM; Viterbi decoder; coder; convolutional code; decoder; generator polynomials; user data rate; AWGN; Additive noise; Application specific integrated circuits; CMOS technology; Convolutional codes; Costs; Decoding; NASA; Polynomials; Viterbi algorithm;
Conference_Titel :
Military Communications Conference, 1990. MILCOM '90, Conference Record, A New Era. 1990 IEEE
Conference_Location :
Monterey, CA
DOI :
10.1109/MILCOM.1990.117423
