Title :
A 450 MHz 512 kB second-level cache with a 3.6 GB/s data bandwidth
Author :
Bateman, B. ; Freeman, C. ; Halbert, J. ; Hose, K. ; Petrie, G. ; Reese, E.
Author_Institution :
Intel Corp., Hillsboro, OR, USA
Abstract :
This 512 kB, 4-way set-associative cache SRAM for a processor is configurable as a 512 k, or larger, second-level cache using one or more cache chips. Speed between the processor and cache in separate packages is achieved by communicating over an independent source-synchronous 72 b data bus. Power is reduced by semi-synchronous design. Supply voltage is 2.5 V and maximum core power is 4.5 W at 450 MHz assuming back-to-back reads. The 0.35 /spl mu/m CMOS process features 4-level metal and a 0.22 /spl mu/m Leff.
Keywords :
cache storage; 0.35 micron; 2.5 V; 3.6 GB/s; 4.5 W; 459 MHz; 512 kB; CMOS process; back-to-back reads; data bandwidth; independent source-synchronous data bus; maximum core power; second-level cache; semi-synchronous design; set-associative cache SRAM; Bandwidth; Built-in self-test; Circuits; Clocks; Decoding; Hoses; Packaging; Random access memory; Testing; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-4344-1
DOI :
10.1109/ISSCC.1998.672528
