Non volatile memory reliability prediction based on oxide defect generation rate during stress and retention tests

This paper shows how Floating Gate (FG) memory cells behavior during retention tests can be predicted relying on static electrical stress tests. Retention tests are usually performed at High or Low Temperature Bake (HTB or LTB respectively) to provide warning of an impending failure of the memory cell capability to store data. Retention tests are very useful to screen out defective cell populations but induce significant test time overhead. To overcome this limitation, a correlation between stress and retention time is established to anticipate retention test results. Moreover, further investigations are made to provide a physical explanation for the correlation. Indeed, it is shown that the same FG memory tunnel oxide traps are activated during electrical stress tests (high electric field) and retention tests (low electric field).