Title :
A 1.8 ns access, 550 MHz 4.5 Mb CMOS SRAM
Author :
Nambu, H. ; Kanetani, K. ; Yamasaki, K. ; Higeta, K. ; Usami, M. ; Kusunoki, T. ; Yamaguchi, K. ; Homma, N.
Author_Institution :
Central Res. Lab., Hitachi Ltd., Kokubunji, Japan
Abstract :
High-speed, high-density 4-4.5Mb CMOS cache SRAMs do not have speed comparable to that of a 4.5Mb BiCMOS SRAM. This 4.5Mb CMOS SRAM has access time equivalent to that of a BiCMOS SRAM. Key techniques for achieving this speed are a decoder using source-coupled-logic (SCL) circuits combined with reset circuits, a sense amplifier with nMOS source followers, and a sense-amplifier activation-pulse generator that uses a duplicate memory-cell array.
Keywords :
CMOS memory circuits; SRAM chips; cache storage; cellular arrays; decoding; 1.8 ns; 4.5 Mbit; 550 MHz; CMOS; access time; cache SRAMs; duplicate memory-cell array; nMOS source followers; reset circuits; sense amplifier; sense-amplifier activation-pulse generator; source-coupled-logic; BiCMOS integrated circuits; Clocks; Decoding; Delay effects; MOS devices; Power dissipation; Pulse amplifiers; Pulse generation; Random access memory; Space vector pulse width modulation;
Conference_Titel :
Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-4344-1
DOI :
10.1109/ISSCC.1998.672529
