DocumentCode
310215
Title
Two-phase asynchronous pipeline control
Author
Appleton, Sam S. ; Morton, Shannon V. ; Liebelt, Michael J.
Author_Institution
Dept. of Electr. & Electron. Eng., Adelaide Univ., SA, Australia
fYear
1997
fDate
7-10 Apr 1997
Firstpage
12
Lastpage
21
Abstract
In this paper the potential speed and power efficiency of two-phase asynchronous systems operating under a bounded-delay model are explored. It is shown that two-phase bounded-delay systems can significantly outperform four-phase approaches published to date. The design of a prototype microprocessor using this two-phase approach is then described, and preliminary results are presented
Keywords
microprocessor chips; pipeline processing; bounded-delay model; prototype microprocessor; two-phase asynchronous pipeline control; Automatic control; Circuits; Control system synthesis; Control systems; Design engineering; Logic; Microprocessors; Pipelines; Power engineering and energy; Power system modeling;
fLanguage
English
Publisher
ieee
Conference_Titel
Advanced Research in Asynchronous Circuits and Systems, 1997. Proceedings., Third International Symposium on
Conference_Location
Eindhoven
Print_ISBN
0-8186-7922-0
Type
conf
DOI
10.1109/ASYNC.1997.587140
Filename
587140
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