DocumentCode
3102546
Title
A high-density SRAM design technique using silicon nanowire FETs
Author
Liao, Yi-Bo ; Chiang, Meng-Hsueh ; Kim, Keunwoo ; Hsu, Wei-Chou
Author_Institution
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
fYear
2011
fDate
7-9 Dec. 2011
Firstpage
1
Lastpage
2
Abstract
A new “all-single-wire” 6T-SRAM technique using junctionless nanowire FETs is proposed. The quantization-free design shows a great advantage in Si-nanowire-based SRAM cells. TCAD-simulated results show that the proposed single-wire SRAM can improve Read stability, and it can save about one third of the area as compared with multi-wire design while it is compatible with conventional processing.
Keywords
SRAM chips; elemental semiconductors; field effect transistors; integrated circuit design; nanowires; silicon; Si; TCAD simulation; all-single-wire 6T-SRAM technique; high-density SRAM design technique; junctionless nanowire FET; multiwire design; quantization-free design; read stability; silicon nanowire FET; FETs; Logic gates; Mathematical model; Nanoscale devices; Random access memory; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Device Research Symposium (ISDRS), 2011 International
Conference_Location
College Park, MD
Print_ISBN
978-1-4577-1755-0
Type
conf
DOI
10.1109/ISDRS.2011.6135407
Filename
6135407
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