A /spl Delta//spl Sigma/PLL for 14 b 50 ksample/s frequency-to-digital conversion of a 10 MHz FM signal

In wireless applications, digital signal processing is increasingly used in place of analog processing to improve reliability, reduce manufacturing cost, and allow programmability. Usually, the requisite A/D conversion is performed after the RF signal is down-converted to an intermediate frequency (IF) in the 0-100 MHz range, and the demodulation is digital. Design simplifications, such as the avoidance of in-phase and quadrature analog processing, can often be achieved if the A/D conversion is above 5 MHz, but in CMOS technology such systems are usually limited to about 12 b precision. This key component of a CMOS frequency-to-digital converter (FDC), a device that simultaneously performs A/D conversion and frequency demodulation, in certain cases, promises to be an attractive alternative to conventional non-zero IF A/D conversion.