Title :
Application of output prediction logic to differential CMOS
Author :
Kio, Su ; Mcmurchie, Larry ; Sechen, Carl
Author_Institution :
Washington Univ., Seattle, WA, USA
Abstract :
We apply the output prediction logic (OPL) technique to the differential CMOS logic family. Including the effects of process, voltage and temperature (PVT) variations, we show that OPL differential CMOS is more than 40% faster than the single-rail OPL-dynamic logic family, and nearly 5 times faster than optimized static CMOS. We also demonstrate an OPL-differential 64:2 compressor that is 37% faster than the OPL-dynamic version. Finally, we show that OPL-differential is nearly twice as fast as differential domino
Keywords :
CMOS logic circuits; cellular arrays; data compression; logic gates; CMOS logic; OPL-differential 64:2 compressor; differential CMOS; output prediction logic; process variations; temperature variations; voltage variations; CMOS logic circuits; CMOS process; Circuit synthesis; Delay; Inverters; Logic circuits; Logic gates; Switches; Temperature; Voltage;
Conference_Titel :
VLSI, 2001. Proceedings. IEEE Computer Society Workshop on
Conference_Location :
Orlando, FL
Print_ISBN :
0-7695-1056-6
DOI :
10.1109/IWV.2001.923140
