Title :
A linear threshold gate implementation in single electron technology
Author :
Lageweg, Casper ; Cotofana, Sorin ; Vassiliadis, Stamatis
Author_Institution :
Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
Abstract :
In this paper we focus on the design of threshold logic functions in Single Electron Tunneling (SET) technology, using the tunnel junction´s specific behavior i.e., the ability to control the transport of individual electrons. We introduce a novel design of an n-input linear threshold gate which can accommodate both positive and negative weights and built-in signal amplification, using 1 tunnel junction and n+2 true capacitors. As an example we present a 4-input threshold gate with both positive and negative weights
Keywords :
Boolean functions; adders; logic design; logic gates; single electron transistors; threshold logic; 4-input threshold gate; SET technology; built-in signal amplification; linear threshold gate implementation; n-input linear threshold gate; negative weights; positive weights; single electron tunnelling technology; threshold logic functions; Capacitors; Delay estimation; Electrons; Logic circuits; Logic design; Logic functions; Signal design; Switches; Threshold voltage; Tunneling;
Conference_Titel :
VLSI, 2001. Proceedings. IEEE Computer Society Workshop on
Conference_Location :
Orlando, FL
Print_ISBN :
0-7695-1056-6
DOI :
10.1109/IWV.2001.923145
