Quasi-optimum Efficiency in Output Voltage Hysteretic Control for a Buck Switching Converter with Wide Load Range

Successful on-chip integration of a buck switching power converter for battery-operated portable applications concurrently requires fulfilling stringent specifications, namely low silicon area occupancy, low relative output ripple, proper transient response whilst assuring high efficiency for a wide range of load currents. This latter key characteristic of high efficiency can be achieved not only by the power plant design but by the use of proper control methods. This work focuses in efficiency optimization of a buck converter suited to CMOS integration. Switching and conduction energy loss models are first discussed both for continuous and discontinuous conduction modes. Minimization of overall power losses yields an optimum law that continuously tunes the switching frequency as a function of load current. Being one of the simplest control methods applied to a buck converter the output voltage hysteretic control, the work then focuses in the implicit switching frequency tuning that results from the application of this control method and its impact on overall power efficiency. The paper contrasts the analytical models for the frequency variation, matched with system-level simulations, when including as non-idealities both output capacitor ESR and control delay. It is observed that for low output current values, the output voltage hysteretic control provides quasi-optimum power efficiency. Design criteria for matching both explicit optimum law and the law implicit in hysteretic control are provided, and a design procedure including output voltage ripple and capacitor value is discussed. Numerical examples throughout the paper consider a standard CMOS 0.35 mum technology. Experimental results for a low frequency prototype demonstrate the implicit switching frequency modulation of the output voltage hysteretic control