DocumentCode
3102815
Title
A low power SIMD architecture for affine-based texture mapping
Author
Badawy, Wael
Author_Institution
Dept. of Electr. & Comput. Eng., Calgary Univ., Alta., Canada
fYear
2001
fDate
37012
Firstpage
129
Lastpage
132
Abstract
This paper presents a novel low power SIMD architecture for texture mapping using transformation. Low power has been achieved by exploring the properties of the affine transformation to reduce the computational cost. The architecture has been prototyped using 0.35 μm CMOS technology with three layers of metal. The proposed architecture can be used in video object motion tracking and texture warping processors
Keywords
CMOS digital integrated circuits; digital signal processing chips; image texture; low-power electronics; object recognition; parallel architectures; video signal processing; 0.35 micron; CMOS technology; affine-based texture mapping; computational cost; low power SIMD architecture; texture warping processors; video object motion tracking; CMOS technology; Computational efficiency; Computer architecture; Costs; Drives; Equations; Performance analysis; Prototypes; Technical Activities Guide -TAG; Topology;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI, 2001. Proceedings. IEEE Computer Society Workshop on
Conference_Location
Orlando, FL
Print_ISBN
0-7695-1056-6
Type
conf
DOI
10.1109/IWV.2001.923151
Filename
923151
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