A New Approach to Maximizing the Power Handling Capability in Recessed-Gate Silicon Carbide Static Induction Transistors

Author

Choi, Y.C. ; Cha, H.-Y. ; Chandrashekhar, M. ; Eastman, L.F. ; Spencer, M.G.

Author_Institution

Sch. of Electr. & Comput. Eng., Cornell Univ., Ithaca, NY

fYear

2005

fDate

16-16 June 2005

Firstpage

2171

Lastpage

2174

Abstract

For a recessed gate SiC SIT, a new approach to solve a breakdown voltage specific on-resistance trade-off problem and consequently achieve an extremely high power capability was presented. Simulations were fully performed to analyze the influence of critical design parameters on the device power performance. They showed that the basic trade-off was successfully eliminated if the depth of a JFET diffusion layer was greater than 1.35 times the gate trench depth, due to the effective suppression of the JFET resistance. Consequently, the proposed device architecture showed much higher power capability than the conventional structure, suggesting that device power performance be maximized by implementing a JFET diffusion layer in a conventional SiC SIT, with a narrow half-width of a source region

Keywords

electric breakdown; junction gate field effect transistors; silicon compounds; static induction transistors; JFET diffusion layer; JFET resistance; SiC; breakdown voltage; gate silicon carbide static induction transistors; gate trench depth; power handling capability; Analytical models; Annealing; Computational modeling; Doping profiles; Electrodes; FETs; Performance analysis; Roentgenium; Silicon carbide; Thermal conductivity;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Electronics Specialists Conference, 2005. PESC '05. IEEE 36th

Conference_Location

Recife

Print_ISBN

0-7803-9033-4

Type

conf

DOI

10.1109/PESC.2005.1581933

Filename

1581933