Title :
A hybrid wave-pipelined network router
Author :
Delgado-Frias, José G. ; Nyathi, Jabulani
Author_Institution :
Dept. of Electr. & Comput. Eng., Virginia Univ., Charlottesville, VA, USA
Abstract :
In this paper a novel hybrid wave-pipelined bit-pattern associative router is presented. A router is an important component in communication network systems. The bit-pattern associative router (BPAR) allows for flexibility and can accommodate a large number of routing algorithms. Wave-pipelining is a high performance approach which implements pipelining in logic without using intermediate registers. In this study a hybrid wave-pipelined approach has been proposed and implemented. Hybrid wave-pipelining allows for the reduction of the delay difference between the maximum and minimum delays by narrowing the gap between each stage of the system. This approach yields narrow “computing cones” that allow faster clocks to be run. This is the first study in wave-pipelining that deals with a system that has a substantially different set of pipeline stages. The bit-pattern associative router has three stages: condition match, selection function, and port assignment. Each stage´s data delay paths are tightly controlled to optimize the proper propagation of signals. The simulation results show that using hybrid wave-pipelining significantly reduces the clock period and circuit delays become the limiting factor, preventing further clock cycle time reduction
Keywords :
VLSI; circuit layout CAD; content-addressable storage; delays; integrated circuit layout; integrated memory circuits; network routing; pipeline processing; timing; VLSI router; bit-pattern associative router; clock cycle time reduction; clock period reduction; condition match; data delay paths; delay difference; dynamic CAM cell; hybrid wave-pipelined network router; port assignment; routing algorithms; selection function; Circuits; Clocks; Communication networks; Communication system control; Delay effects; Logic; Network topology; Pipeline processing; Propagation delay; Routing;
Conference_Titel :
VLSI, 2001. Proceedings. IEEE Computer Society Workshop on
Conference_Location :
Orlando, FL
Print_ISBN :
0-7695-1056-6
DOI :
10.1109/IWV.2001.923156