Title :
Interface optimization for improved routability in chip-package-board co-design
Author :
Meister, Tilo ; Lienig, Jens ; Thomke, Gisbert
Author_Institution :
Inst. of Electromech. & Electron. Design, Dresden Univ. of Technol., Dresden, Germany
Abstract :
The simultaneous optimization of both pin assignment and pin routing for different hierarchy levels (chip, package, board) of an electronic system is a bottleneck in today´s hierarchical co-design flows, typically requiring manual optimization strategies and multiple iterations. Specifically, a fast and finegrained evaluation of routability that considers all requirements between the different hierarchy levels is missing. In this paper we provide a comprehensive, fast method to evaluate the routability of interfaces in hierarchical systems based on a new probabilistic routability prediction. We implemented our methodology in an industrial design flow and achieved significant improvement in overall routing, including reduced manufacturing costs of chip-package-board co-designs.
Keywords :
circuit optimisation; integrated circuit design; integrated circuit packaging; printed circuits; probability; chip-package-board co-design; hierarchical system; industrial design flow; interface optimization; manufacturing cost; probabilistic routability prediction; routability; Accuracy; Optimization; Pins; Prediction methods; Probabilistic logic; Routing; Tin;
Conference_Titel :
System Level Interconnect Prediction (SLIP), 2011 13th International Workshop on
Conference_Location :
San Diego, CA
Print_ISBN :
978-1-4577-1240-1
DOI :
10.1109/SLIP.2011.6135430
