Novel Power Loss Limit Analysis Method for High-speed, Ultra-low Loss Power Converter

Novel power loss limit analysis method has been developed for designing future high-speed, ultra-low loss converters. The concept of the method is consisted by 3 parts. They are (1) power loss measurement with a circuit stray parameter adjustable circuit board, (2) separation of power loss into power loss factors by using measurement results and (3) parameter extraction of power loss factors. Advantages of the proposed method are power loss limit estimation under practically operating conditions and a high OPD converter design including influences of circuit stray parameters. To verify an effectiveness of the method, power device loss in a high-speed switching chopper circuit constructed with a Si-MOSFET and a SiC-SBD has been analyzed. The method has successfully extracted power loss factors. Characteristics of power loss factors are modeled by using analysis results. A power device loss limit model is newly established based on power loss factors. Power device losses have been predicted by using the power device loss model. The predicted power device losses are in good agreement with the power losses measured by experiments