DocumentCode
3103136
Title
Table of content
fYear
2011
fDate
5-5 June 2011
Firstpage
1
Lastpage
3
Abstract
The following topics are dealt with: TSV scaling and 3D FPGA; multicore and embedded SoC design; advanced techniques on routing; TSV-based 3D IC; and power network resource estimation and design.
Keywords
field programmable gate arrays; integrated circuit interconnections; network routing; system-on-chip; three-dimensional integrated circuits; 3D FPGA; TSV scaling; TSV-based 3D IC; embedded SoC design; power network resource design; power network resource estimation; routing;
fLanguage
English
Publisher
ieee
Conference_Titel
System Level Interconnect Prediction (SLIP), 2011 13th International Workshop on
Conference_Location
San Diego, CA
Print_ISBN
978-1-4577-1240-1
Type
conf
DOI
10.1109/SLIP.2011.6135438
Filename
6135438
Link To Document