Title :
A high speed analog 50 Ω line driver in digital CMOS technology
Author :
Payne, Robert F. ; Connelly, J.Alvin
Author_Institution :
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
A single-ended analog buffer designed to drive 50 Ω loads is described. The circuit consists of a common source output pair driven by a pair of differential error amplifiers which significantly reduce the output impedance. This technique improves the drive capability of operational amplifiers. This paper demonstrates the feasibility of using the circuit technique as a stand alone buffer. The amplifier has been fabricated in a 2 μm digital CMOS technology and occupies an area of 190 mil2. The amplifier has a ~50 Ω output impedance and an upper half power frequency of 23 MHz when driving a 50 Ω/50 pF load and consumes 102 mW from ±5 V supplies
Keywords :
CMOS analogue integrated circuits; buffer circuits; differential amplifiers; driver circuits; operational amplifiers; 102 mW; 2 micron; 23 MHz; 5 V; 50 ohm; 50 pF; common source output pair; differential error amplifiers; digital CMOS technology; drive capability; operational amplifiers; output impedance; single-ended analog buffer; stand alone buffer; upper half power frequency; Analog circuits; Bandwidth; CMOS analog integrated circuits; CMOS technology; Circuit testing; Differential amplifiers; Impedance; Integrated circuit technology; Operational amplifiers; Rails;
Conference_Titel :
Circuits and Systems, 1996., IEEE 39th Midwest symposium on
Conference_Location :
Ames, IA
Print_ISBN :
0-7803-3636-4
DOI :
10.1109/MWSCAS.1996.594018
