A novel high-speed parallel multiply-accumulate arithmetic architecture employing modified radix-4 signed-binary recoding

This paper presents a high-speed fully signed-binary (SE) parallel multiply-accumulate (MAC) arithmetic architecture. This arithmetic architecture employs a novel 5-digit overlapped scanning technique for the modified radix-4 recoding of the constituent SE multiplier. The proposed scanning technique permits a reduction in the number of the intermediate partial product components generated during the course of MAC arithmetic operation by a factor of two, leading to a fast processing speed at reduced hardware cost. The resulting MAC arithmetic architecture performs full-precision accumulation, rounding, and overflow correction concurrently in order to facilitate a high-speed overall operation. A high-performance architecture is also presented for IEEE Standard 754 default rounding of the final SE MAC result. The proposed MAC arithmetic architecture is parameterized for ASIC implementations using the Actel 1.2 μ technology parameters, and is subsequently verified by using Viewlogic simulations