Fast externally asynchronous-internally clocked systems: implementation and analysis of a new genre of self-timed circuits

Defying the timing defects and limitations imposed on traditional asynchronous circuits, the externally asynchronous internally clocked (EAIC) system provides the digital designer with a new tool for constructing self-timed circuits. Based on revolutionary memory unit, the EAIC architecture lends itself nicely to sequential design, where a typical EAIC system may require less power, use less hardware, and operate at much greater speeds than comparable synchronous designs. This paper describes the analysis of several circuits and culminates with a comparison of EAIC systems versus synchronous designs