A controller chip for a scaleable ATM switch node

This paper presents the architecture of the control chip for an Asynchronous Transfer Mode (ATM) chipset, used in a distributing banyan network. This chip, with 4 switch chips, forms a scaleable 16×16 switching element that runs at 155 MHz. It is larger and much more efficient than previous switching nodes. The architecture uses shared multibuffering, since it is less bandwidth limited than a shared buffering switch. Such criteria make the switch more scaleable, although the control logic increases in complexity. Very high performance is required of the chip and thus a number of special circuits have been created to achieve this performance. The chip has been prototyped in 1.0 micron CMOS using a mixture of static and dynamic logic