• DocumentCode
    3104159
  • Title

    A Versatile Digital Pulsewidth Modulation Architecture with Area-Efficient FPGA Implementation

  • Author

    Foley, Raymond F. ; Kavanagh, Richard C. ; Marnane, William P. ; Egan, Michael G.

  • Author_Institution
    Dept. of Electr. & Electron. Eng., Univ. Coll. Cork
  • fYear
    2005
  • fDate
    16-16 June 2005
  • Firstpage
    2609
  • Lastpage
    2615
  • Abstract
    This paper describes a multi-output digital pulsewidth modulator (DPWM) that generates versatile waveforms suitable for use in a typical multi-phase interleaved switching DC-DC buck converter. A heterogenous DPWM is proposed that achieves a resolution of 255 ps, facilitating multi-megahertz switching frequencies. A novel global architecture is also introduced that exploits the phased nature of the interleaved buck converter, limiting the number of required multiplexers/comparators and enabling a large, adjustable number of variable-frequency pulsewidth modulated outputs to be generated using a small, xed architecture with programmable duty-cycles and dead-times
  • Keywords
    DC-DC power convertors; PWM power convertors; comparators (circuits); field programmable gate arrays; switching convertors; area-efficient FPGA implementation; digital pulsewidth modulation architecture; multiplexers-comparators; programmable duty-cycles; switching DC-DC buck converter; variable-frequency PWM; waveform generation; Buck converters; Digital modulation; Field programmable gate arrays; Multiplexing; Phase modulation; Pulse generation; Pulse modulation; Pulse width modulation converters; Space vector pulse width modulation; Switching frequency;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Power Electronics Specialists Conference, 2005. PESC '05. IEEE 36th
  • Conference_Location
    Recife
  • Print_ISBN
    0-7803-9033-4
  • Type

    conf

  • DOI
    10.1109/PESC.2005.1582001
  • Filename
    1582001