A Design and Implementation of High-Speed 3DES Algorithm System

Author

Jun, Yang ; Na, Li ; Jun, Ding

Author_Institution

Sch. of Inf. Sci. & Eng., Yunnan Univ., Kunming, China

fYear

2009

fDate

13-14 Dec. 2009

Firstpage

175

Lastpage

178

Abstract

This paper introduces the principle of 3DES encryption algorithm and the detailed description of the algorithm design and implementation on FPGA. For the improvement of the S-box, it uses a single S-box to replace the original eight S-boxes. This will not only greatly reduces the size of circuit but also reduces the power consumption of the entire circuit. In the design, pipelining technology is used to improve its running speed. All the modules are using Verilog HDL hardware description language to achieve, and at last it is downloaded to the FPGA chip.

Keywords

cryptography; field programmable gate arrays; hardware description languages; 3DES encryption algorithm; FPGA chip; S-box; Verilog HDL hardware description language; data encryption standard; high-speed 3DES algorithm system; pipelining technology; power consumption; Algorithm design and analysis; Circuits; Cryptography; Design engineering; Energy consumption; Field programmable gate arrays; Hardware design languages; Iterative algorithms; Pipeline processing; Security; 3DES; DES; FPGA; Pipeline; Verilog HDL;

fLanguage

English

Publisher

ieee

Conference_Titel

Future Information Technology and Management Engineering, 2009. FITME '09. Second International Conference on

Conference_Location

Sanya

Print_ISBN

978-1-4244-5339-9

Type

conf

DOI

10.1109/FITME.2009.49

Filename

5380903