Verification of synthesized circuits at register transfer level with flow graphs

Presents a new approach to the verification of automatically synthesized register transfer structures. Horizontal verification is performed on the flow graph which is largely a syntax independent representation of behavior. After extracting a flow graph from the register transfer structure by symbolic simulation, the extracted and the specified flow graphs are normalized into a normal form. A comparison of the normalized flow graphs gives the proof of correctness. The various synthesis steps have been classified into five classes and the normalization procedures have been evaluated