Title :
A 240 Mb/1 W CMOS EPRML read channel LSI for hard disk drives
Author :
Matsuura, T. ; Nara, T. ; Komatsu, T. ; Imaizumi, E. ; Matsutsuru, T. ; Horita, R. ; Katsu, H. ; Suzumura, S. ; Sato, K.
Author_Institution :
Semicond. & Integrated Circuits Div., Hitachi Ltd., Tokyo, Japan
Abstract :
A 3.3 V 1 W 240 Mb/s EPRML read/write channel LSI for hard disk drives uses 0.4 /spl mu/m CMOS technology. Analog implementation of the entire channel has lower power consumption, because it eliminates the power-consuming A/D converter. It requires a BiCMOS process for precise analog circuits. The digital approach uses an A/D converter that provides precise digital signal processing. Here, the CMOS digital approach is used because it has potential for advanced signal processing. Two important issues are 1) reduction of the power consumption of extensive digital circuits and the A/D converter, and 2) breaking the speed bottleneck of the A/D converter. To reduce power consumption, a 0.4 /spl mu/m CMOS process with 3.3 V supply voltage is used. In addition, 3.3 V analog CMOS circuits are used, such as a gain controlled integrator for 7th-order equiripple active filters and an analog PLL.
Keywords :
CMOS integrated circuits; analogue-digital conversion; hard discs; large scale integration; mixed analogue-digital integrated circuits; 0.4 micron; 1 W; 240 Mbit/s; 3.3 V; A/D converter; ADC; CMOS EPRML read channel LSI; CMOS digital circuits; analog CMOS circuits; analog PLL; equiripple active filters; gain controlled integrator; hard disk drives; power consumption reduction; read/write channel LSI; Analog circuits; BiCMOS integrated circuits; CMOS process; CMOS technology; Digital circuits; Digital signal processing; Energy consumption; Hard disks; Large scale integration; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-4344-1
DOI :
10.1109/ISSCC.1998.672546