An approach to the analysis and test of crosstalk faults in digital VLSI circuits

The continuous reduction of the device size in integrated circuits and the increasing of the switching rate cause parasitic capacitances between conducting layers which might become dominant enough to provoke logic errors in the circuits. So, capacitive couplings can be considered as potential logic faults. Classical fault models do not cover this sort of faults. This paper presents a logic fault characterization of these faults, a logic level circuit fault model, a crosstalk fault list generator working at layout level and a test pattern generation procedure for crosstalk type faults