Circuit partitioning for waveform relaxation

Author

John, W. ; Rissiek, W. ; Paap, K.L.

Author_Institution

Cadlab-Joint Venture Univ. of Paderborn, Germany

fYear

1991

fDate

25-28 Feb 1991

Firstpage

149

Lastpage

153

Abstract

New partitioning strategies for the simulation of bipolar circuits using the waveform relaxation method are presented. On the one hand concepts known from layout-generation and node tearing simulation are used. On the other hand the hierarchical structure of the circuit description list and a minimal-cut criterion is used to find a good partitioning. With the help of these new partitioning algorithms it is possible for the first time to simulate large bipolar circuits using waveform relaxation. The applicability of the algorithms is demonstrated by the simulation of real-life circuits

Keywords

VLSI; bipolar integrated circuits; circuit analysis computing; digital simulation; circuit description list; hierarchical structure; minimal-cut criterion; node tearing simulation; partitioning algorithms; partitioning strategies; simulate large bipolar circuits; simulation of bipolar circuits; simulation of real-life circuits; waveform relaxation; Circuit simulation; Computational modeling; Coupling circuits; Feedback circuits; Information systems; International collaboration; MOSFET circuits; Partitioning algorithms; Relaxation methods; Transient analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation. EDAC., Proceedings of the European Conference on

Conference_Location

Amsterdam

Type

conf

DOI

10.1109/EDAC.1991.206379

Filename

206379