A 600 MHz CMOS PLL microprocessor clock generator with a 1.2 GHz VCO

Author

von Kaenel, V. ; Aebischer, D. ; van Dongen, R. ; Piguet, Christian

Author_Institution

XEMICS SA, Neuchatel, Switzerland

fYear

1998

fDate

5-7 Feb. 1998

Firstpage

396

Lastpage

397

Abstract

A clock multiplier for the 600 MHz 72 W (estimated) CMOS Alpha microprocessor is presented. The supply voltage of the analog part of the PLL (VDDA) is provided by an on-chip voltage regulator with a decoupling capacitance. The 3.3 V supply is used to generate the quieter internal supply voltage needed for the sensitive analog part of the PLL and allows the regulator to operate properly even if the 3.3 V supply is noisy. A bandgap voltage reference is used to generate an internal reference for the supply voltage of 2.2 V. The regulator PSRR is always larger than 20 dB in the frequency range of the power supply noise, reducing the noise amplitude on the analog-supply voltage. The minimum measured supply voltage for the regulator is 2.5 V with a regulated output of 2.2 V (without noise generator).

Keywords

CMOS integrated circuits; clocks; microprocessor chips; mixed analogue-digital integrated circuits; phase locked loops; reference circuits; timing circuits; voltage-controlled oscillators; 1.2 GHz; 2.2 V; 2.5 V; 3.3 V; 600 MHz; 72 W; CMOS Alpha microprocessor; CMOS PLL clock generator; UHF VCO; bandgap voltage reference; clock multiplier; decoupling capacitance; microprocessor clock generator; onchip voltage regulator; Capacitance; Clocks; Microprocessors; Noise generators; Noise level; Noise reduction; Phase locked loops; Photonic band gap; Regulators; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-4344-1

Type

conf

DOI

10.1109/ISSCC.1998.672550

Filename

672550