An adaptive digital deskewing circuit for clock distribution networks

As clock frequency in CPU designs increases, skew management in the clock network becomes more important. Clock skew reduces the performance of the design and is a function of load, network distribution across the die, and device mismatch as well as temperature, and voltage gradients. This digital deskewing circuit can be used in microprocessor designs to equalize two clock distribution spines by compensating for these mismatches and gradients. The circuit is composed of delay lines in both spines of the microprocessor clock distribution network, a phase detection circuit, and a controller. The phase detection circuit determines the phase relationship between the two spines and generates an output based on the phase relationship. The controller takes the phase detection information and makes a discrete adjustment to one of the delay lines that was determined by the controller to require adjustment.