A noise-immune GHz-clock distribution scheme using synchronous distributed oscillators

In the near future, microprocessor clock frequencies will go beyond 1 GHz. In GHz microprocessors, a single phase-locked loop (PLL) is difficult to use since the delay in distributing and buffering the clock from the single PLL is more than 1 clock cycle. A multiple-PLL method that distributes many PLLs on a chip solves this problem, but significantly increases the skew and jitter induced by noise. The authors present a scheme for clock distribution comprising a single-PLL with multiple outputs. The PLL is constructed of a phase frequency detector, a charge pump, a low pass filter, and voltage-controlled oscillators. A test chip is fabricated using a 0.25 /spl mu/m CMOS technology.