Title :
A noise-immune GHz-clock distribution scheme using synchronous distributed oscillators
Author :
Mizuno, H. ; Ishibashi, Koji
Author_Institution :
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
Abstract :
In the near future, microprocessor clock frequencies will go beyond 1 GHz. In GHz microprocessors, a single phase-locked loop (PLL) is difficult to use since the delay in distributing and buffering the clock from the single PLL is more than 1 clock cycle. A multiple-PLL method that distributes many PLLs on a chip solves this problem, but significantly increases the skew and jitter induced by noise. The authors present a scheme for clock distribution comprising a single-PLL with multiple outputs. The PLL is constructed of a phase frequency detector, a charge pump, a low pass filter, and voltage-controlled oscillators. A test chip is fabricated using a 0.25 /spl mu/m CMOS technology.
Keywords :
CMOS digital integrated circuits; clocks; digital phase locked loops; jitter; microprocessor chips; synchronisation; timing circuits; voltage-controlled oscillators; 0.25 micron; 1 GHz; CMOS technology; GHz microprocessors; VCO; charge pump; low pass filter; microprocessor clock frequencies; multiple output single PLL; noise-immune GHz-clock distribution scheme; phase frequency detector; single phase-locked loop; synchronous distributed oscillators; voltage-controlled oscillators; CMOS technology; Charge pumps; Clocks; Delay; Jitter; Low pass filters; Microprocessors; Phase frequency detector; Phase locked loops; Voltage-controlled oscillators;
Conference_Titel :
Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-4344-1
DOI :
10.1109/ISSCC.1998.672558