Title :
TAS: an accurate timing analyser for CMOS VLSI
Author :
Hajjar, A. ; Marbot, R. ; Greiner, A. ; Kiani, P.
Author_Institution :
Bull SA, Les Clayes-sous-Bois, France
Abstract :
A CMOS timing analyser using accurate delay models is presented. Switch-level analytic delays are derived from I/V characteristics of short-channel MOSFETS. A significant improvement in accuracy is obtained from the analysis of pertinent capacitances, modeling conflicts and slope effects in CMOS gates. The program handles large-scale circuits and gives the worst-case delays between circuit terminals in realistic CPU times. The algorithm for path analysis is described. It is concluded that the run time is linear with the number of transistors, the accuracy within 5% over a wide range of design types
Keywords :
CMOS integrated circuits; VLSI; automatic testing; circuit analysis computing; digital integrated circuits; integrated circuit testing; integrated logic circuits; CMOS VLSI; CMOS gates; I/V characteristics; TAS; capacitances; delay models; large-scale circuits; modeling conflicts; path analysis; short-channel MOSFETS; slope effects; switch level analytic delays; timing analyser; Algorithm design and analysis; Capacitance; Central Processing Unit; Circuits; Delay; Large-scale systems; MOSFETs; Semiconductor device modeling; Timing; Very large scale integration;
Conference_Titel :
Design Automation. EDAC., Proceedings of the European Conference on
Conference_Location :
Amsterdam
DOI :
10.1109/EDAC.1991.206404
