DocumentCode
3106256
Title
Hybrid BIST based on weighted pseudo-random testing: a new test resource partitioning scheme
Author
Jas, Abhijit ; Krishna, C.V. ; Touba, Nur A.
Author_Institution
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
fYear
2001
fDate
2001
Firstpage
2
Lastpage
8
Abstract
This paper presents a new test resource partitioning scheme that is a hybrid approach between external testing and BIST. It reduces tester storage requirements and tester bandwidth requirements by orders of magnitude compared to conventional external testing, but requires much less area overhead than a full BIST implementation providing the same fault coverage. The proposed approach is based on weighted pseudo-random testing and uses a novel approach for compressing and storing the weight sets. Three levels of compression are used to greatly reduce test costs. No test points or any modifications are made to the function logic. The proposed scheme requires adding only a small amount of additional hardware to the STUMPS architecture. Experimental results comparing the proposed approach with other approaches are presented
Keywords
VLSI; application specific integrated circuits; automatic test pattern generation; built-in self test; fault diagnosis; integrated circuit testing; logic testing; STUMPS architecture; area overhead; fault coverage; hybrid BIST; test costs; test resource partitioning scheme; tester bandwidth requirements; tester storage requirements; weighted pseudo-random testing; Bandwidth; Built-in self-test; Circuit faults; Circuit testing; Costs; Fault detection; Hardware; Logic testing; System-on-a-chip; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 19th IEEE Proceedings on. VTS 2001
Conference_Location
Marina Del Rey, CA
Print_ISBN
0-7695-1122-8
Type
conf
DOI
10.1109/VTS.2001.923409
Filename
923409
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