Title :
A hierarchical approach to timing verification in CMOS VLSI design
Author :
Yang, H.G. ; Holburn, D.M.
Author_Institution :
Dept. of Eng., Cambridge Univ., UK
Abstract :
The author describes a novel hierarchical approach to timing verification. Four types of relationship existing among signal paths are distinguished, based on a classification of the degree of interdependency in the circuit. In this way, irrelevant path delays can be excluded through consideration of the interaction between critical paths and others. Furthermore, under suitable conditions, bounded delay values for large hierarchical systems can be deduced using bounded delays determined for their constituent cells. Finally, the authors discuss the impact on design strategy of the hierarchical delay model presented in this paper
Keywords :
CMOS integrated circuits; VLSI; circuit analysis computing; integrated circuit technology; integrated logic circuits; logic CAD; CMOS VLSI design; bounded delay values; critical paths; hierarchical delay model; timing verification; Circuit simulation; Computational modeling; Computer simulation; Delay effects; Delay estimation; Digital systems; Hierarchical systems; Propagation delay; Timing; Very large scale integration;
Conference_Titel :
Design Automation. EDAC., Proceedings of the European Conference on
Conference_Location :
Amsterdam
DOI :
10.1109/EDAC.1991.206405
