Robust and low-cost BIST architectures for sequential fault testing in datapath multipliers

The modified Booth array multiplier is the most ubiquitous multiplier architecture in the datapaths of either general purpose microprocessors or specialized Digital Signal Processors. Sequential fault testing for Booth array multipliers has never been proposed in the past. In this paper, we present two BIST architectures for modified Booth array multipliers with respect to the Realistic Sequential Cell Fault model (RS-CFM). The first BIST architecture aims to resolve the test invalidation problem to the largest possible extent, while the second one aims to test cost reduction. Both BIST architectures achieve very high sequential fault coverage and impose moderate hardware and delay overhead. Simplified variations of the two BIST architectures are also presented for the non-recoded signed array multipliers. Thus, the proposed BIST architectures offer a universal BIST solution that covers the totality of signed array multipliers: non-recoded and recoded