DocumentCode :
3106310
Title :
Clock independent timing verification of level-sensitive latches
Author :
Tjärnström, Robert
Author_Institution :
Dept. of Phys. & Meas. Technol., Linkoping Univ., Sweden
fYear :
1991
fDate :
25-28 Feb 1991
Firstpage :
271
Lastpage :
275
Abstract :
The author presents a method to automatically handle level-sensitive latches in timing analysis/verification. Timing specifications, including delays and timing constraints, are automatically generated for the cells in the design. The generated timing specifications are independent of clocking strategy, since clock and data are treated equally. Conditional constraints and paths are used to capture the transparent property of latches. The constraint rules are based on electrical/physical laws instead of assumptions about design styles. Timing errors due to clock skew and improper design are detected
Keywords :
circuit analysis computing; delays; logic circuits; clock skew; constraint rules; delays; digital CMOS; level-sensitive latches; timing analysis; timing constraints; timing error detection; timing specifications; Circuit simulation; Clocks; Delay; Driver circuits; Latches; Physics; Pins; Shift registers; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation. EDAC., Proceedings of the European Conference on
Conference_Location :
Amsterdam
Type :
conf
DOI :
10.1109/EDAC.1991.206406
Filename :
206406
Link To Document :
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