Title :
On improving the accuracy of multiple defect diagnosis
Author_Institution :
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Abstract :
Logic defect diagnosis locates the defect spots in a digital IC that fail testing. It is one of the critical steps during the process of manufacturing yield improvement. Automatic defect diagnosis techniques for circuits with single defects have been improved significantly. However, the techniques for multiple defect diagnosis are still inadequate. In this paper, we propose an effective heuristic for diagnosing a full-scan design with multiple defects. Concepts called curable vectors and curable outputs are incorporated. By combining these two measures as a grading criterion, each signal´s possibility of being one of the defect spots is calculated with a high accuracy. Experimental results on ISCAS85 benchmark circuits indicate that the proposed method indeed outperforms the conventional heuristics
Keywords :
automatic testing; boundary scan testing; fault diagnosis; integrated circuit testing; integrated circuit yield; logic testing; ISCAS85 benchmark circuits; curable outputs; curable vectors; full-scan design; grading criterion; heuristic; logic defect diagnosis; manufacturing yield improvement; multiple defect diagnosis; Benchmark testing; Cause effect analysis; Circuit faults; Circuit testing; Databases; Dictionaries; Digital integrated circuits; Integrated circuit testing; Logic testing; Manufacturing processes;
Conference_Titel :
VLSI Test Symposium, 19th IEEE Proceedings on. VTS 2001
Conference_Location :
Marina Del Rey, CA
Print_ISBN :
0-7695-1122-8
DOI :
10.1109/VTS.2001.923415