• DocumentCode
    3106382
  • Title

    MACHETE: synthesis of sequential machines for easy testability

  • Author

    Vinnakota, Bapiraju ; Jha, Niraj K.

  • Author_Institution
    Dept. of Electr. Eng., Princeton Univ., NJ, USA
  • fYear
    1991
  • fDate
    25-28 Feb 1991
  • Firstpage
    289
  • Lastpage
    293
  • Abstract
    Test generation for sequential machines is known to be computationally expensive. The authors present a scheme, called MACHETE (MACHines for Easy TEstability), for synthesizing easily testable architectures for sequential machines by adding some state transitions and their associated output vectors to the state transition table. This is done to make the internal states of the machine easily controllable as well as observable. This can enable us to obtain a high fault coverage in reasonable amounts of CPU time
  • Keywords
    logic CAD; logic testing; sequential machines; FSM, finite state machines; MACHETE; high fault coverage; sequential machines; state transition graph; test generation; testability; testable architectures; Automata; Clocks; Encoding; Integrated circuit testing; Logic testing; Pins; Sequential analysis; Shift registers;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation. EDAC., Proceedings of the European Conference on
  • Conference_Location
    Amsterdam
  • Type

    conf

  • DOI
    10.1109/EDAC.1991.206410
  • Filename
    206410