A process and technology-tolerant IDDQ method for IC diagnosis

The use of I_DDQ test as a defect reliability screen has been widely used to improve device quality. However, the increase in subthreshold leakage currents in deep submicron technologies has made it difficult to set an absolute pass/fail threshold. Recent work has focused on strategies that calibrate for process and/or technology-related variation effects. In this paper, a new I_DDQ technique is proposed that is based on an extension of a V_DDT-based method called Transient Signal Analysis (TSA). The method, called Quiescent Signal Analysis or QSA, uses the I_DDQs measured at multiple supply pins as a means of localizing defects. Increases in I_DDQ due to a defect are regionalized by the resistive element of the supply grid. Therefore, each supply pin sources a unique fraction of the total I_DDQ drawn by the defect. The method analyzes the regional I_DDQs and “triangulates” the position of the defect to an (x,y) location in the layout. This information can be used in combination with fault dictionary-based techniques as a means of further resolving the defect´s location