Title :
RT-level fault simulation based on symbolic propagation
Author :
Sinanoglu, Ozgur ; Orailoglu, Alex
Author_Institution :
Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
Abstract :
The rapid rise in size and complexity of VLSI circuits has stimulated a need to handle fault simulation at higher levels of abstraction. We outline an RT-level fault simulation technique that utilizes symbolic data to group fault effects. Experimental results show that the proposed methodology provides superior speed-ups and accurate fault coverages
Keywords :
VLSI; circuit simulation; fault simulation; high level synthesis; logic simulation; symbol manipulation; RT-level fault simulation; VLSI circuits; complexity; fault coverages; fault effects; speed-ups; symbolic data; symbolic propagation; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Computer science; Computer simulation; Hardware; Instruments; Time to market; Very large scale integration;
Conference_Titel :
VLSI Test Symposium, 19th IEEE Proceedings on. VTS 2001
Conference_Location :
Marina Del Rey, CA
Print_ISBN :
0-7695-1122-8
DOI :
10.1109/VTS.2001.923445
