Self-testable pipelined ADC with low hardware overhead

Author

Peralías, Eduardo J. ; Huertas, Gloria ; Rueda, Adoración ; Huertas, José L.

Author_Institution

IMSE, Seville Univ., Spain

fYear

2001

fDate

2001

Firstpage

272

Lastpage

277

Abstract

This paper presents a BIST scheme for the structural testing of pipelined ADCs. The operational principle relies on testing every ADC stage reconfigured as an A/D-D/A block and applying as input a set of analog DC values. These values have been determined as the appropriate and simple stimuli giving a single output signature. A new output signature is proposed allowing a low-cost digital domain test evaluation. The new technique is intended to be used in pipelined converters of an arbitrary number of conversion stages and provided with a digital correction mechanism

Keywords

analogue-digital conversion; automatic testing; built-in self test; integrated circuit testing; monolithic integrated circuits; pipeline processing; BIST scheme; analog DC values; digital correction mechanism; low hardware overhead; low-cost digital domain test evaluation; pipelined A/D converters; pipelined ADC; self-testable ADC; single output signature; structural testing; Built-in self-test; Consumer electronics; Costs; Hardware; Maintenance; Manufacturing industries; Microelectronics; Production; Test equipment; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 19th IEEE Proceedings on. VTS 2001

Conference_Location

Marina Del Rey, CA

Print_ISBN

0-7695-1122-8

Type

conf

DOI

10.1109/VTS.2001.923450

Filename

923450