DocumentCode
3107041
Title
Enabling embedded memory diagnosis via test response compression
Author
Chen, John T. ; Rajski, Janusz ; Khare, Jitendra ; Kebichi, Omar ; Maly, Wojciech
Author_Institution
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
fYear
2001
fDate
2001
Firstpage
292
Lastpage
298
Abstract
This paper introduces a method that enables failure diagnosis of BISTed memories by compression of test responses. This method has been tested by simulation of memories with various specifications, fail patterns and test algorithms. The proposed method has been implemented in 0.18 μ CMOS IC
Keywords
CMOS memory circuits; built-in self test; failure analysis; integrated circuit testing; process monitoring; random-access storage; 0.18 micron; BISTed memories; CMOS; embedded memory diagnosis; fail patterns; failure diagnosis; test algorithms; test response compression; test responses; Automatic testing; Built-in self-test; CMOS process; Circuit testing; Graphics; Hardware; Laser feedback; Pins; Random access memory; Read-write memory;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 19th IEEE Proceedings on. VTS 2001
Conference_Location
Marina Del Rey, CA
Print_ISBN
0-7695-1122-8
Type
conf
DOI
10.1109/VTS.2001.923452
Filename
923452
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