Title :
A modified clock scheme for a low power BIST test pattern generator
Author :
Girard, P. ; Guiller, L. ; Landrault, C. ; Pravossoudovitch, S. ; Wunderlich, H.-J.
Author_Institution :
LIRMM, Univ. des Sci. et Tech. du Languedoc, Montpellier, France
Abstract :
In this paper, we present a new low power test-per-clock BIST test pattern generator that provides test vectors which can reduce the switching activity during test operation. The proposed low power/energy BIST technique is based on a modified clock scheme for the TPG and the clock tree feeding the TPG. Numerous advantages can be found in applying such a technique during BIST
Keywords :
automatic test pattern generation; built-in self test; clocks; integrated circuit testing; logic testing; low-power electronics; TPG; clock tree; low power BIST test pattern generator; modified clock scheme; switching activity; test operation; test vectors; Batteries; Built-in self-test; CMOS technology; Circuit testing; Clocks; Costs; Energy consumption; System testing; Test pattern generators; Uniform resource locators;
Conference_Titel :
VLSI Test Symposium, 19th IEEE Proceedings on. VTS 2001
Conference_Location :
Marina Del Rey, CA
Print_ISBN :
0-7695-1122-8
DOI :
10.1109/VTS.2001.923454
