• DocumentCode
    3107112
  • Title

    The development of FPGA architectures for primitive operator digital filter implementations

  • Author

    Arslan, T. ; Eskikurt, H.I. ; Horrocks, D.H.

  • Author_Institution
    Sch. of Eng., Univ. of Wales Coll. of Cardiff, UK
  • fYear
    1996
  • fDate
    35408
  • Firstpage
    42430
  • Lastpage
    42435
  • Abstract
    An architecture for a primitive operator FPGA is proposed in this paper. The performance of two CALB architectures, CALB1 and CALB2, has been investigated in terms of their operation speed and chip area. The CALB 1 architecture offers the advantage of faster speed of operation whereas the CALB2 architecture offers the advantage of reduced chip area
  • Keywords
    field programmable gate arrays; CALB architectures; CALB1; CALB2; FPGA architectures; chip area; operation speed; primitive operator digital filter;
  • fLanguage
    English
  • Publisher
    iet
  • Conference_Titel
    Digital and Analogue Filters and Filtering Systems (Digest No. 1996/238), IEE Colloquium on
  • Conference_Location
    London
  • Type

    conf

  • DOI
    10.1049/ic:19961264
  • Filename
    600635
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3107112