Design and FPGA verification of HF RFID transponder

A new design technique and FPGA verification of digital core of 13.56 MHZ (HF) RFID Transponder based on ISO-15693 standard is presented. The digital core is used for decoding the incoming signal, executing commands and sending the data back to the reader. The digital core consists of two parts, Transmitter and Receiver which include Decoding module, Manchester encoding module, crc16 check module and control module. We have implemented 1 out of 4 decoding technique with one sub-carrier frequency in this paper. The results are verified in the specified clock frequency in xc2vp4-6fg256 device in FPGA Xilinx kit using VHDL in RTL level.