Design and FPGA verification of HF RFID transponder

Author

Parhi, S.S. ; Venkateswaran, P. ; Nandi, R.

Author_Institution

Dept. of Electron. & Tele-Commun. Eng., Jadavpur Univ., Kolkata, India

fYear

2012

fDate

28-29 Dec. 2012

Firstpage

421

Lastpage

424

Abstract

A new design technique and FPGA verification of digital core of 13.56 MHZ (HF) RFID Transponder based on ISO-15693 standard is presented. The digital core is used for decoding the incoming signal, executing commands and sending the data back to the reader. The digital core consists of two parts, Transmitter and Receiver which include Decoding module, Manchester encoding module, crc16 check module and control module. We have implemented 1 out of 4 decoding technique with one sub-carrier frequency in this paper. The results are verified in the specified clock frequency in xc2vp4-6fg256 device in FPGA Xilinx kit using VHDL in RTL level.

Keywords

ISO standards; decoding; field programmable gate arrays; hardware description languages; radiofrequency identification; transponders; FPGA Xilinx kit; FPGA verification; HF RFID transponder; ISO-15693 standard; Manchester encoding module; RTL level; VHDL level; control module; crc16 check module; decoding module; digital core; frequency 13.56 MHz; receiver; signal decoding; sub-carrier frequency; transmitter; xc2vp4-6fg256 device; Decoding; Field programmable gate arrays; Frequency modulation; Hafnium; Indexes; Table lookup; Transponders; CRC16-CCITT; FPGA; ISO-15693; Manchester Encoding; RFID Transponder; XC2VP4-6FG256;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, Devices and Intelligent Systems (CODIS), 2012 International Conference on

Conference_Location

Kolkata

Print_ISBN

978-1-4673-4699-3

Type

conf

DOI

10.1109/CODIS.2012.6422228

Filename

6422228