The optimized strategy for input current harmonic of low switching frequency PWM rectifier

The industry application of High-power medium-voltage drives converter is an appealing spot in Power electronics technology in recent years. This paper presents an optimized control strategy for input current harmonic of rectifier of three-level NPC back-to-back converter under low switching frequency conditions. A modified P-N SVPWM method includes asymmetrical regular sampling, even-order harmonic elimination and natural DC bus balancing is applied for optimize the THD performance of input currents. And a modified proportional sinusoidal signal integrator method based on control scheme in two phase stationary reference frame which is different from ordinary direct-quadrature (DQ) rotating reference frame is proposed. It provides a specific input current harmonic elimination performance especially considerable in low switching frequency circumstance. Simulation and experimental results based on a rectifier of a 75kVA three-level NPC back-to-back converter prototype with a 400Hz device switching frequency constraint show satisfactory performance.