Optimization techniques for multiple output function synthesis

Author

Buonanno, G. ; Sciuto, D. ; Stefanelli, R.

Author_Institution

Dipartimento di Elettronica, Politecnico di Milano, Italy

fYear

1991

fDate

25-28 Feb 1991

Firstpage

545

Lastpage

551

Abstract

Design of multiple outputs CMOS combinational gates is considered. Two techniques for the minimization of multiple output functions at the switching level are introduced. These techniques are based on innovative transistor interconnection structures named Delta and Lambda networks. A branch and bound algorithm to be used for complex gate synthesis is presented. Design examples are also provided. It is shown that the two techniques can be combined together, if necessary, to obtain further area reductions

Keywords

CMOS integrated circuits; combinatorial circuits; combinatorial switching; integrated logic circuits; logic design; logic gates; minimisation of switching nets; switching functions; trees (mathematics); CMOS combinational gates; Delta networks; Lambda networks; area reductions; branch/bound algorithm; complex gate synthesis; minimization; multiple output function synthesis; optimisation techniques; switching level; transistor interconnection structures; CMOS technology; Circuit synthesis; Integrated circuit interconnections; Inverters; Joining processes; Legged locomotion; MOSFETs; Minimization methods; Network synthesis; Signal synthesis;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation. EDAC., Proceedings of the European Conference on

Conference_Location

Amsterdam

Type

conf

DOI

10.1109/EDAC.1991.206467

Filename

206467