DocumentCode :
3107287
Title :
Periodic signal suppression in a concurrent fault simulator
Author :
Weber, Tara ; Somenzi, Fabio
Author_Institution :
Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
fYear :
1991
fDate :
25-28 Feb 1991
Firstpage :
565
Lastpage :
569
Abstract :
Clock suppression has been proposed to take advantage of the periodic signals such as the clock present in synchronous designs. In clock suppression, no events due to the clock input are generated, but the information can be reconstructed as needed. In this paper, the authors present periodic signal suppression, which is a generalized form of clock suppression, as a means to suppress predictable events of all periodic signals throughout the circuit. To do this, a special signal state labeled P is introduced. P states indicate that signals are periodic, but cause no unnecessary activity in an event driven simulator. At any time, the original waveform can be reconstructed from the periodic signal. This general implementation allows clock suppression to work on divided or gated clocks and on signals that may alternate periodic and non-periodic behavior in addition to the clock tree. Moreover, concurrent simulation of faults on the suppressed signal wires including the clock tree is possible
Keywords :
circuit analysis computing; fault location; logic CAD; logic testing; clock suppression; clock tree; concurrent fault simulator; creator; divided clocks; gated clocks; logic design; periodic signals; signal suppression; synchronous designs; Circuit faults; Circuit simulation; Circuit testing; Clocks; Computational modeling; Discrete event simulation; Logic testing; Signal design; Signal processing; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation. EDAC., Proceedings of the European Conference on
Conference_Location :
Amsterdam
Type :
conf
DOI :
10.1109/EDAC.1991.206471
Filename :
206471
Link To Document :
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