Title :
An evaluation of pseudo random testing for detecting real defects
Author :
Tseng, Chao-Wen ; Mitra, Subhasish ; Davidson, Scott ; McCluskey, Edward J.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Stanford Univ., CA, USA
Abstract :
Research has shown that single stuck-at fault (SSF) N-detect test sets are effective for detecting defects not modeled by the SSF model. Experimental results showed N-detect coverage is a good metric for determining test quality. In this paper, we examine the test quality of pseudo-random Built-in-Self-Test (BIST) patterns by quantifying the relations between their N-detect coverage and test length. We theoretically derive bounds on the minimum test length of pseudo-random patterns required to achieve a given N-detect coverage. For faults with high detectability, the expected test length for N-detection is around N times the expected test length for single detection. However, for faults with low detectability, the expected test length for N-detection can be NlogN times the expected test length for detecting the fault only once; this increases the test length significantly. We also introduce the idea of effective detectability which is important for analyzing the effectiveness of BIST techniques for detecting real defects
Keywords :
VLSI; automatic testing; built-in self test; fault diagnosis; integrated circuit testing; BIST patterns; detectability; effective detectability; expected test length; minimum test length; pseudo random testing; pseudo-random patterns; single stuck-at fault; test quality; Automatic testing; Built-in self-test; Chaos; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Integrated circuit testing; Production; Test pattern generators;
Conference_Titel :
VLSI Test Symposium, 19th IEEE Proceedings on. VTS 2001
Conference_Location :
Marina Del Rey, CA
Print_ISBN :
0-7695-1122-8
DOI :
10.1109/VTS.2001.923469