Low-power-consumption 10-Gbps GaAs 8:1 multiplexer/1:8 demultiplexer

Author

Yoshida, N. ; Fujii, M. ; Atsumo, T. ; Numata, K. ; Asai, S. ; Kohno, M. ; Oikawa, H. ; Tsutsui, H. ; Maeda, T.

Author_Institution

Optoelectron. & High Frequency Device Res. Labs., NEC Corp., Tsukuba, Japan

fYear

1997

fDate

12-15 Oct. 1997

Firstpage

113

Lastpage

116

Abstract

An ECL-compatible 10-Gbps GaAs 8:1 multiplexer (MUX) and 1:8 demultiplexer (DEMUX) has been developed. To decrease power consumption and to maximize phase margin, the clock-generating circuit employs source-coupled FET logic (SCFL) circuits. Also, cascade-connected source-follower circuits are used in the clock buffer. These circuits can reduce the power consumption when the fan-out number is large. Direct coupled FET logic (DCFL) circuits are employed for the 2:1 MUX/1:2 DEMUX circuits operating below 5 Gbps. The ICs, which are mounted on ceramic packages, operate at up to 10 Gbps with a power consumption of 1.2 W for the MUX and 1.0 W for the DEMUX at ECL-compatible supply voltages. These power-consumption values are one-third of the previously reported values.

Keywords

III-V semiconductors; demultiplexing equipment; direct coupled FET logic; emitter-coupled logic; field effect integrated circuits; gallium arsenide; multiplexing; multiplexing equipment; 1.0 W; 1.2 W; 10 Gbit/s; DCFL circuit; ECL compatibility; GaAs; GaAs multiplexer/demultiplexer; MUX/DEMUX IC; SCFL circuit; cascade-connected source-follower circuit; ceramic package; clock buffer; clock-generating circuit; fan-out number; phase margin; power consumption; Ceramics; Clocks; Coupling circuits; Energy consumption; FETs; Gallium arsenide; Logic circuits; Multiplexing; Packaging; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1997. Technical Digest 1997., 19th Annual

Conference_Location

Anaheim, CA, USA

ISSN

1064-7775

Print_ISBN

0-7803-4083-3

Type

conf

DOI

10.1109/GAAS.1997.628250

Filename

628250